The present invention relates generally to memory and more particularly to handling memory requests.
The more components of the memory controller used, the deeper a pipeline for processing a memory request is considered. Deeper processing pipelines are associated with more latency due to the added processing used to propagate memory requests through the processing pipeline. Read requests to access data from RAM are generally processed through a deep processing pipeline of the memory controller. Memory controller components that make up the processing pipeline are used to handle requests from various clients. The memory controller components organize memory requests to deal with request dependencies, in which some memory requests are to be processed before others. The components also prioritize some memory requests over others. However, to reduce the amount of time taken in processing, some memory controller components may be bypassed.
Bypassing memory controller components to reduce latency is known. However, clients must be provided with a large amount of information. Clients are provided information to decide whether or not to bypass various memory controller components. Various operating parameters of the memory controller components usually need to be known in order to allow the components to be bypassed by a particular client. Only components that are idle or have no other memory requests to process may be bypassed. A client is generally provided with information regarding the memory being accessed, particular pages, which are currently open, physical addresses and memory configurations. Memory controller systems provide clients with enough information regarding particular memory configurations and the status of the memory controller components before the client may decide to allow a particular memory request to be bypassed. The need to transfer such a large amount of information reduces the efficiency with memory request bypassing since the information is transferred to the client for every request to be bypassed. This problem becomes further complicated when the memory controller includes asynchronous components, such as due to memory using a separate clock. From the above discussion it should be apparent that an improved method is needed for providing bypassing for memory requests.